1. Field of the Invention
The present invention relates in general to the field of modern electronic digital systems with increasing complexity, and in particular to a latch arrangement for such an electronic digital system, and a corresponding method for implementing a latch arrangement. Still more particularly, the present invention relates to a data processing program and a computer program product for implementing a latch arrangement.
2. Description of the Related Art
In modern electronic digital systems, like Central Processing Units (CPUs), with increasing complexity sophisticated functions are implemented to gain still more performance improvements. Some of these functions need to be flexible and not be finally fixed in hardware. So the hardware behavior can be modified with switches and it is not always required to design and/or manufacture a new chip layout when a modification of the hardware behavior is required.
For the modification of the hardware behavior process configuration-switch latches are used. The configuration-switch latches are latches that can be modified by shift operation, but do not change their value once the processor is in normal operation. Typically such configuration-switch latches were used during bring-up and testing of the electronic digital system, but mostly not for normal operation at customer side. Now with the increasing complexity of the electronic digital systems the number of such configuration-switch latches is increasing too and the configuration-switch latches are used for final hardware also. With that also Reliability, Availability and Serviceability (RAS) requirements for the configuration-switch latches need to be considered, which was not necessary when the configuration-switch latches were used during bring-up and/or testing of the electronic digital systems only.
For implementing of the Reliability, Availability and Serviceability (RAS) coverage with configuration-switch latches two strategies are known. A first strategy uses special latches which are hardened against hardware fail. This improves the Reliability, Availability and Serviceability (RAS) coverage at the cost of chip area since these latches are much larger than normal latches and the chance for an undetected error is only reduced. A second strategy uses extra configuration-switch parity latches for protection of groups of these configuration-switch latches. This delivers better Reliability, Availability and Serviceability (RAS) coverage, but has the disadvantage of making the different configuration-switch latches dependent to each other. During simulation and bring-up this often causes problems, since the parity needs to be set according to the value of all configuration-switch latches in one group and so one configuration-switch latch cannot be set independent of the other configuration-switch latches.
In U.S. Pat. No. 5,633,882 “ERROR DETECTION AND CORRECTION CIRCUIT” by Babb et al. an error detection and correction circuit is disclosed. The disclosed error detecting and correcting circuit comprises a check bit output latch which stores check bits generated by a check bit generator and outputs the newly generated check bits to memory when a single error occurs in the word located in the check bits. The data is corrected so the newly generated check bits are correct and can be latched out to memory at the same time the data is latched out. Additionally the error detecting and correcting circuit includes a syndrome generator, an error corrector, and an error detector. The described error detecting and correcting circuit provides error detection and correction circuits correcting check bits in memory with newly generated check bits when no errors in the data word are detected.
In U.S. Pat. No. 6,590,929 B1 “METHOD AND SYSTEM FOR RUN-TIME LOGIC VERIFICATION OF OPERATIONS IN DIGITAL SYSTEMS” by Williams a method and system for run-time logic verification of operations in digital systems are disclosed. The disclosed system for controllable run-time verification of operations in a logic structure of a digital system comprises a controllable bit stream generator having means for producing a controlled bit stream output, which corresponds to a bit sequence instantiating a verification of operations within the logic structure; means for coupling the controlled bit stream output to the logic structure, wherein the logic structure includes a data array coupled via a plurality of logic gates to an error correcting code encoder which detects and corrects a single bit error in the data; and means for verifying the operations of the logic structure utilizing the controlled bit stream output. The verifying means include means for instantiating a generation of the controlled bit stream output wherein a sequence of bits represents the data; and means for sending the controlled bit stream output to the plurality of logic gates.